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The PCI Bus Power Management Interface Specification is a new specification developed to enhance the base PCI Bus Revision 2.1 architecture to include standardized power management capabilities. Intel chaired the PCISIG Power Management Workgroup, receiving key contributions from other PCISIG member companies including Texas Instruments, IBM, Compaq, and Adaptec. The new specification is architecturally aligned with the ACPI specification, and as such, enables PCI devices, both motherboard and add-in, to participate in platform-wide operating system-directed power management.
PCI Engineering Change Request - Addition of 3.3Vaux signal to Connector
The PCI SIG Power Management Working Group has determined that in order to enable PCI bus power management to the full extent that the PCI Bus Power Management Interface Specification, Intel’s Instantly Available PC and Microsoft's OnNow initiatives allow, PCI add-in devices need a dedicated and guaranteed source of power to keep the wake event card logicactive while the rest of the PCI bus is without power. This ECR defines a previously reserved connector pin (14A is proposed) as a 3.3Vaux voltage supply to provide the standard source of power for wake event logic.
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